Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are synthesis, placement, routing, and timing analysis of the system on the target device.
Silicon devices used for target devices have seen the trends of more aggressive performance targets and dropping supply voltages from generation to generation. Transistor threshold voltages have not been keeping up with the dropping supply voltages. As a result, transistors are not turned on as well as they have been in the past, which in turn means that the delays of gates and buffers are growing more sensitive to supply voltage changes. Increased path delay variation manifests as increased cycle-to-cycle delay variation, otherwise known as jitter. Jitter is a form of timing uncertainty that acts to reduce timing margins which are continually shrinking as performance targets are increased.
It is important to model the impact of jitter on timing margins. In particular, what is needed is a model flexible enough to cover two usage scenarios. The first scenario involves designers working with characterized field programmable gate array (FPGA) silicon. These designers expect timing analysis to report accurate and conservative timing margins that allow them to evaluate design options such as performance targets, input output placement, clocking strategies, and registering and placement of intellectual property (IP) blocks. Part of this analysis will include estimates of jitter accumulation along clock and data paths that are customized to the FPGA configurations being studied. The second scenario involves FPGA architects evaluating sets of features to offer in future generations of FPGA. These architects require reasonable predictions of timing margins to evaluate alternative structures and to assess whether features justify their area, power, and design effort costs.